LS830 TO-71 6L ROHS

LS830 LS831 LS832 LS833 ULTRA LOW LEAKAGE LOW DRIFT MONOLITHIC DUAL N-CHANNEL JFET AMPLIFIER FEATURES ULTRA LOW DRIFT │ΔVGS1-2/ΔT│= 5µV/ºC max. ULTRA LOW NOISE IG=80fA TYP. LOW NOISE en=70nV/√Hz TYP. LOW CAPACITANCE CISS=3pf max. ABSOLUTE MAXIMUM RATINGS NOTE 1 @ 25°C (unless otherwise noted) Maximum Temperatures Storage Temperature -55 to +150°C Operating Junction Temperature -55 to +150°C Maximum Voltage and Current for Each Transistor NOTE 1 -VGSS Gate Voltage to Drain or Source 40V -VDSO Drain to Source Voltage 40V -IG(f) Gate Forward Current 10mA -IG Gate Reverse Current 10µA Top View SOIC Top View TO-71 & TO-78 Maximum Power Dissipation @ TA = 25ºC Continuous Power Dissipation (Total) 500mW SYMBOL CHARACTERISTIC MIN. TYP. MAX. UNITS BVGSS Breakdown Voltage -40 -60 -- V CONDITIONS VDS= 0 IG= -1nA BVGGO Gate-to-Gate Breakdown ±40 -- -- V IG= ±1µA ID= 0 IS = 0 TRANSCONDUCTANCE gfss Full Conduction 70 300 500 µS VDG= 10V VGS= 0 f = 1kHz gfs Typical Operation 50 100 200 µS VDG= 10V ID= 30µA f = 1kHz │gfs1-2/gfs│ Differential -- 1 5 % VDG= 10V VGS= 0 DRAIN CURRENT IDSS Full Conduction 60 400 1000 µA │IDSS1-2/IDSS│ Differential at Full Conduction -- 2 5 % ELECTRICAL CHARACTERISTICS TA = 25ºC (unless otherwise noted) SYMBOL CHARACTERISTIC │ΔVGS1-2/ΔT│max. Drift vs. Temperature LS830 LS831 LS832 LS833 UNITS 5 10 20 75 µV/ºC CONDITIONS VDG = 10V ID = 30µA TA = -55ºC to +125ºC │VGS1-2│max. Offset Voltage 25 25 25 25 mV -IG typical Operating 0.1 0.1 0.1 0.5 pA -IG typical High Temperature 0.1 0.1 0.1 0.5 nA TA= +125ºC IGSS typical At Full Conduction 0.2 0.2 0.2 1.0 pA VGS = 20V, VGS = 0V IGSS typical High Temperature 0.5 0.5 0.5 1.0 nA VGS = 0 VDG = 10V ID = 30µA VGS = 20V TA= +125ºC Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 201127 03/03/2020 Rev#A7 ECN# LS830 LS831 LS832 LS833 SYMBOL CHARACTERISTIC MIN. TYP. MAX. UNITS CONDITIONS -0.6 -2 -4.5 V VDS= 10V ID= 1nA -- -- -4 V VDG= 10V ID= 30µA -- 1 -- pA VGG= ±20V ID = IS = 0A GATE-SOURCE VGS(off) Cutoff Voltage VGS Operating Range GATE CURRENT IGGO Gate-to-Gate Leakage OUTPUT CONDUCTANCE gOSS Full Conduction -- -- 5 µS VDG= 10V VGS= 0 gOS Operating -- -- 0.5 µS VDG= 10V ID= 30µA │gOS 1-2│ Differential -- -- 0.1 µS COMMON MODE REJECTION CMRR -20 log │ΔVGS1-2/ ΔVDS│ -- 90 -- dB ΔVDS= 10 to 20V ID=30µA CMRR -20 log │ΔVGS1-2/ ΔVDS│ -- 90 -- dB ΔVDS= 5 to 10V ID=30µA -- -- 1 dB VDS= 10V VGS= 0 f= 100Hz NBW= 6Hz NOISE NF Figure en Voltage -- 20 70 nV/√Hz VDG= 10V RG=10MΩ ID= 30µA f= 10Hz NBW= 1Hz CAPACITANCE CISS Input -- -- 3 pF VDS= 10V VGS= 0 f= 1MHz CRSS Reverse Transfer -- -- 1.5 pF VDS= 10V VGS= 0 f= 1MHz CDD Drain-to-Drain -- -- 0.1 pF VDG= 10V ID= 30µA TO-71 TO-78 P-DIP 0.210 0.170 SOIC Note: All Dimensions in inches NOTES: 1. These ratings are limiting values above which the serviceability of any semiconductor may be impaired Information furnished by Linear Integrated Systems is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems. Linear Integrated Systems (LIS) is a 25-year-old, third-generation precision semiconductor company providing high-quality discrete components. Expertise brought to LIS is based on processes and products developed at Amelco, Union Carbide, Intersil and Micro Power Systems by company President John H. Hall. Hall, a protégé of Silicon Valley legend Dr. Jean Hoerni, was the director of IC Development at Union Carbide, Co-Founder and Vice President of R&D at Intersil, and Founder/President of Micro Power Systems. Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 201127 03/03/2020 Rev#A7 ECN# LS830 LS831 LS832 LS833